The present invention relates to a method of manufacturing a semiconductor device, and, more particularly, to a method of manufacturing a high frequency (HF) low-noise element such as a gallium arsenide (GaAs) field effect transistor (FET).
Some methods for forming a HF low-noise element such as a GaAs FET, in which a gate length and a channel length must be precisely determined, are conventionally known.
FIGS. 1A to 1D show one of these methods. Referring to these figures, a gate metal film 12 of a refractory metal such as TiW is formed on a GaAs substrate 11. Then, a photoresist pattern 13 is formed on the gate metal film 12 (FIG. 1A). The gate metal film 12 is patterned using the photoresist pattern 13 as a mask to form a gate electrode 12G (FIG. 1B). Thereafter, silicon is ion-implanted in the GaAs substrate 11 using the photoresist pattern 13 and gate electrode 12G as a mask. The ion-implanted silicon is activated by annealing to form n.sup.+ -type source and drain regions 14 and 15 (FIG. 1C). Then, in order to provide proper respective distances (or spaces) between the gate electrode 12G and the n.sup.+ -type source and drain regions 14 and 15, the gate electrode 12G is side-etched to positions indicated by dotted lines 16 (FIG. 1D). This side-etching is performed for the following reasons. In a GaAs FET, in order to form a Schottky junction between a gate electrode and a GaAs substrate, a metal electrode is formed on a substrate (i.e., the gate electrode 12 formed on the GaAs substrate 11). In this case, if the gate electrode 12G is formed to be in contact with or in the vicinity of the n.sup.+ -type source and drain regions 14 and 15, a breakdown voltage of an element becomes undesirably low. In order to prevent such a problem, proper respective distances must be provided between the gate electrode 12G and the n.sup.+ -type source and drain regions 14 and 15. Therefore, the side-etching described above is performed.
However, in the above manufacturing method shown in FIGS. 1A to 1D, it is difficult to precisely control the above side-etching. In the worst case, the gate electrode 12G may become disconnected after etching. Furthermore, in an ion-implantation process, the surface of the substrate is bombarded by ions to become roughened and a damaged layer is formed thereon. In an annealing process of an ion-implanted impurity for activation, the gate electrode 12G reacts with the GaAs substrate 11. Then, Schottky characteristics are degraded, or As in the GaAs substrate 11 is evaporated, thereby causing degradation of the semiconductor's characteristics.
A method shown in FIGS. 2A to 2F can solve these problems. A silicon nitride (Si.sub.3 N.sub.4) film as a protection film 17 is formed on a GaAs substrate 11 by plasma chemical vapor deposition (CVD). A first photoresist film 18 is deposited on the film 17. Then, a silicon oxide (SiO.sub.2) film 19 is formed on the photoresist film 18 by sputtering CVD. A second photoresist pattern 20 is formed on the SiO.sub.2 film 19. Then, a multilayer comprising the first photoresist film 18 and the SiO.sub.2 film 19 is patterned using the second photoresist pattern 20 as a mask (FIG. 2B). Thereafter, silicon is ion-implanted in the GaAs substrate 11 using a multilayer of the first photoresist film 18, the SiO.sub.2 film 19 and the second photoresist pattern 20 as a mask so as to form n.sup.+ -type source and drain regions 14 and 15 defining a channel of a predetermined length Lch therebetween, as shown in FIG. 2B. Subsequently, the first photoresist film 18 is side-etched to positions indicated by the dotted lines 21 (FIG. 2C). A silicon oxide film 22 is formed on the Si.sub.3 N.sub.4 film 17 using the photoresist film 18 as a mask (FIG. 2D). Then, the first photoresist film 18 is removed by etching using the silicon oxide film 22 as a mask. By this etching, the overlying SiO.sub.2 film 19 and second photoresist pattern 20 are also removed. At this time, annealing for impurity activation is performed. When the Si.sub.3 N.sub.4 film 17 is subsequently etched using the silicon oxide film 22 as a mask, an opening H is formed in a portion of the Si.sub.3 N.sub.4 film 17 corresponding to a region on which the photoresist film 18 was formed (FIG. 2E). A metal film is formed on the Si.sub.3 N.sub.4 film 17 and is patterned, whereby a gate electrode 23 having a predetermined gate length Lg is formed to be in contact with the substrate 11 through the opening H (FIG. 2F).
According to the manufacturing method shown in FIGS. 2A to 2F, some problems can be prevented by the presence of the protection film 17. In other words, formation of a damaged layer on the surface of the substrate 11 by ion-implantation or annealing, degradation of Schottky characteristics caused by a reaction between the gate electrode 23 and the substrate 11, evaporation of As from the substrate 11, and the like can be prevented. However, in this case, the precision of the gate length Lg depends on that of the side-etching. Since the side-etching cannot be precisely controlled, it is difficult to precisely determine the respective distances between the gate electrode 23, and the n.sup.+ -type source and drain regions 14 and 15.
There is conventionally provided a method shown in FIGS. 3A to 3B for precisely controlling the respective distances between the gate electrode 23, and the n.sup.+ -type source and drain regions 14 and 15. According to this method, first, a gate electrode 23 having a predetermined gate length Lg is formed on a GaAs substrate 11 (FIG. 3A). Then, a silicon nitride film 24 is isotropically formed by plasma CVD so as to cover the gate electrode 23 and the exposed surface of the GaAs substrate 11 (FIG. 3B). In other words, a silicon nitride film 24 having a constant thickness is formed over and around the gate electrode 23 and on the exposed surface of the GaAs substrate 11. The silicon nitride film 24 which is formed on the gate electrode 23 and the substrate 11 is removed by anisotropic etching, e.g., RIE (reactive ion etching), sputtering, ion-milling, or the like so as to leave the silicon nitride film 24 only on the side surfaces of the gate electrode 23 (FIG. 3C). Silicon is ion-implanted in the substrate 11 using the gate electrode 23 and the silicon nitride film 24 remaining on the side surfaces thereof as a mask. Thereafter, the resultant structure is annealed to activate the ion-implanted silicon, whereby source and drain regions 14 and 15 are formed (FIG. 3D).
In the manufacturing method shown in FIGS. 3A to 3D, the thickness of the silicon nitride film 24 formed on the side surfaces of the gate electrode 23 can be precisely controlled. Therefore, the gate length Lg and channel length Lch can be precisely set. Furthermore, the respective distances between the gate electrode 23, and the source and drain regions 14 and 15 can also be precisely set.
However, when the silicon nitride film 24 is etched, a damaged layer is formed on the surface of the substrate 11. Since the gate electrode 23 is in direct contact with the substrate 11, the gate electrode 23 reacts with the GaAs substrate 11 during annealing for impurity activation, whereby Schottky junction characteristics therebetween are degraded, and As is evaporated from the substrate 11.